Within the technology of complementary metal oxide semiconductor (CMOS) transistors, dual stress nitride liners have been used to improve both N-type and P-type transistor performance. As the technology is scaled down, the performance improvement diminishes because the thickness of the stress liner is limited by the pitch size and a phenomenon known as “pinch-off” happens when the pitch size is very small. Pinch off prevents the stressing layer from forming properly, as extremely small pitch sizes provide insufficient room for the stressing layer to form, which can create shear stresses as adjacent stressing layers pinch against one another.